DM9102DEP product brief single chip fast ethernet nic controller may. 2008 rev.1.0 the dm9102d is a fully integrated and cost eff ective single chip fast ethernet nic controller. it is designed with low power and high performan ce process. it is a 2.5/3.3v device with 5v tolerance. the dm9102d provides direct interface to the pci bus and supports bus master mode to achieve the high performance of the pci bus. it fully complies with pci 2.2. in the media side, the dm9102d interfaces to the utp3, 4, 5 in 10base-t and the utp5 in 100base-tx. it is fully compliant with the ieee 802.3u spec. the auto-negotiation and hp auto-mdix function can automatically c onfigure the dm9102d to take the maximum advantage of its abilities. the dm9102d also supports ieee 802.3x?s full-duplex flow control to prevent the receive overflow of link partner. the ipv4 ip/tcp/udp checksum generation and checking can reduce the system cpu utilization. the dm9102d supports two types of power mana gement mechanisms. the main mechanism is based on the onnow architecture, which is required for pc99. the alternative mechanism is based upon the remote wake-on-lan mechanism. block diagram
specifications ? integrated fast ethernet mac, physical layer and transceiver in one chip. ? 128 pin lqfp with cmos process. ? +2.5/3.3v power supply with +5v tolerant i/o. ? comply with pci specification 2.2. ? pci bus master architecture. ? pci bus burst mode data transfer. ? two large independent transmission and receipt fifo . ? up to 256k bytes boot eprom or flash interface. ? eeprom 93c46 interface automatically supports n ode id load and configuration information. ? comply with ieee 802.3u 100base-tx and 802.3 10base-t. ? comply with ieee 802.3u auto-negotiation pr otocol for automatic link type selection. ? support ieee 802.3x full duplex flow control. ? vlan frame length support. ? ip/tcp/udp checksum generation and checking. ? zero copy supporting. ? comply with acpi and pci bus power management. ? support the mii (media independent interface) for an external phy. ? support wake-on-lan function and remote wake-up (magic packet, link change and microsoft ? wake-up frame). ? support 4 wake-on-lan (wol) signals (active high puls e, active low pulse, active high, active low.) ? high performance 100mbps clock generator and data recovery circuit. ? digital clock recovery circuit, using advanced digital algorithm to reduce jitter. ? adaptive equalization circuit and baseline wandering restoration circuit for 100mbps receiver. ? provides loopback mode for easy system diagnostics. ? support hp auto-mdix. ? low power consumption modes: - power reduced mode (cable detection) - power down mode - selectable tx drivers for 1:1 or 1.25:1 transformers for additional power reduction. (1.25:1 transformers for non auto-mdix only).
application voip cpe (ata, ip phone, video phone) ip stb, iptv, ipc, internet radio ip cam, pos, dvr, telecom ordering information part number pin count package dm9102de 128 lqfp DM9102DEP 128 lqfp(pb-free) davicom semiconductor, inc. no.6, li-hsin rd.vi, science pa rk, hsin-chu, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5646929 e-mail: sales@davicom.com.tw
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